Exploiting Signal Skew to Reduce Delay Uncertainty for Chiplet Interconnects

High-bandwidth interconnects between chiplets employ parallel interfaces, whose performance is limited by inter-channel crosstalk. In order to reduce the delay uncertainty (jitter) induced crosstalk, this work analyzes effect of signal skew and proposes a static scheme novel dynamic scheme. A fast algorithm also suggested determine optimal value for The experiment results show that can significantly jitter low-speed buses but fails at high speed. By contrast, reduces about 44% buses, increment due intersymbol interference 71%, effective higher bus rate. proposed schemes require no additional routing overhead.